Current Issue : January - March Volume : 2017 Issue Number : 1 Articles : 5 Articles
High performance computing environment synthesis with\nparallel architecture reconstructing throughout the process itself is\ndescribed. Synthesized computational medium involving Boolean\ndifferential equation calculations so as to function in real-time image\nprocessing. Automaton imaging was illustrated involving the\nrearrangement of every processing medium element to calculate the partial\ndifferentials of n-th order in respect to Boolean function variables. The\nmethod of obtaining setting codes for each element was also described. An\nexample in calculating 2nd -order Boolean derivative to two differentials in\nrespect to Boolean functions, depending on three arguments within the\nreconstructible computational medium of 8x8 processing elements was\ngiven....
This paper proposes a scalable and multi-platform framework for signal acquisition\nand processing, which allows for the generation of acoustic images using planar arrays of MEMS\n(Micro-Electro-Mechanical Systems) microphones with low development and deployment costs.\nAcoustic characterization of MEMS sensors was performed, and the beam pattern of a module, based\non an 8 Ã?â?? 8 planar array and of several clusters of modules, was obtained. A flexible framework,\nformed by an FPGA, an embedded processor, a computer desktop, and a graphic processing unit, was\ndefined. The processing times of the algorithms used to obtain the acoustic images, including signal\nprocessing and wideband beamforming via FFT, were evaluated in each subsystem of the framework.\nBased on this analysis, three frameworks are proposed, defined by the specific subsystems used and\nthe algorithms shared. Finally, a set of acoustic images obtained from sound reflected from a person\nare presented as a case study in the field of biometric identification. These results reveal the feasibility\nof the proposed system....
The motivation of this research was to evaluate the main memory performance of a hybrid\nsuper computer such as the Convey HC-x, and ascertain how the controller performs in several access\nscenarios, vis-� -vis hand-coded memory prefetches. Such memory patterns are very useful in stencil\ncomputations. The theoretical bandwidth of the memory of the Convey is compared with the results\nof our measurements. The accurate study of the memory subsystem is particularly useful for users\nwhen they are developing their application-specific personality. Experiments were performed to\nmeasure the bandwidth between the coprocessor and the memory subsystem. The experiments aimed\nmainly at measuring the reading access speed of the memory from Application Engines (FPGAs).\nDifferent ways of accessing data were used in order to find the most efficient way to access memory.\nThis way was proposed for future work in the Convey HC-x. When performing a series of accesses to\nmemory, non-uniform latencies occur. The Memory Controller of the Convey HC-x in the coprocessor\nattempts to cover this latency. We measure memory efficiency as a ratio of the number of memory\naccesses and the number of execution cycles. The result of this measurement converges to one in most\ncases. In addition, we performed experiments with hand-coded memory accesses. The analysis of the\nexperimental results shows how the memory subsystem and Memory Controllers work. From this\nwork we conclude that the memory controllers do an excellent job, largely because (transparently\nto the user) they seem to cache large amounts of data, and hence hand-coding is not needed in\nmost situations....
Moving object detection including background subtraction and morphological processing is a critical\nresearch topic for video surveillance because of its high computational loading and power\nconsumption. This paper proposes a hardware design to accelerate the computation of background\nsubtraction with low power consumption. A real-time background subtraction method is\ndesigned with a frame-buffer scheme and function partition to improve throughput, and implemented\nusing Verilog HDL on FPGA. The design parallelizes the computations of background update\nand subtraction with a seven-stage pipeline. A stripe-based morphological processing and\naccounting for the completion of detected objects is devised. Simulation results for videos of VGA\nresolutions on a low-end FPGA device show 368 fps throughput for only the real-time background\nsubtraction module, and 51 fps for the whole system, including off-chip memory access. Real-time\nefficiency with low power consumption and low resource utilization is thus demonstrated....
We present a novel remote test system, an integrated remote testing system requiring\nminimal technology support overhead, enabled by configurable analogââ?¬â??digital Integrated Circuits\n(IC) to create a simple interface for a wide range of experiments. Our remote test system requires\nno additional setup, resulting both from using highly configurable devices, as well as from the\nadvancement of straight-forward digital interfaces (i.e., USB) for the resulting experimental system.\nThe system overhead requirements require simple email handling, available over almost all network\nsystems with no additional requirements. The system is empowered through large-scale Field\nProgrammable Analog Array (FPAA) devices and Baseline Tool Framework (BTF), where we present\na range of experimentally measured examples illustrating the range of user interfacing available for\nthe remote user....
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